In general, a diffusion process is performed to form a necessary layer and an annealing process is performed to recover crystalinity and stabilize physical property. During these processes, parameters such as temperature, gas, pressure, and reaction time are controlled to form a necessary layer.
In such a diffusion process, a desirable layer is formed in accordance with the kinds of gas and the thickness of the layer is decided in accordance with the reaction time. After process conditions such as temperature and pressure, are determined, a reaction gas is introduced to form a layer or to diffuse an impurity onto a layer. Since a conventional diffusion process is performed by introducing and simultaneously exhausting a gas (impurity source gas), this leads to a very long process time and a large amount of gas can be consumed. If the process is performed by raising internal temperature of the chamber, the gas is fast dissolved and the amount of dissolved gas increases to shorten the process time. However, as a semiconductor device structure has become highly integrated requiring a shallow junction, there is a limit to use this kind of method.
Recently, a PH.sub.3 annealing process using a sheet-fed or a vertical furnace has been used to increase the capacitance of a semiconductor device.
FIG. 1 is a flow chart showing the steps of an annealing process in accordance with a conventional method for manufacturing a semiconductor device, and FIG. 2 is a diagram for depicting a conventional method for manufacturing a semiconductor device.
Referring to FIGS. 1-2, a conventional semiconductor device manufacturing process is performed by flowing a process gas. As shown in FIG. 2, the process gas is continuously supplied from a process gas supply apparatus 502 into a chamber 500 where a semiconductor manufacturing process is performed, and the supplied process gas is continuously exhausted from the chamber 500 through an exhausting apparatus 504. That is, the conventional semiconductor device manufacturing process is performed with a first valve 510 installed on a supply line 506 combining the process gas supply apparatus 502 with the chamber 500, and a second valve 512 installed on an exhausting line 508 combining the chamber 500 with the exhausting apparatus 504 being opened.
The conventional PH.sub.3 annealing process, as shown in FIG. 1, includes the steps of loading a semiconductor wafer into a chamber (S1000), setting process conditions in the chamber (S1005), forming process gas flow (S1010), performing an annealing process (S1015), then, blocking process gas and purging the inside of the chamber (S1020), dropping internal temperature of the chamber (S1025), and unloading the semiconductor wafer from the chamber (S1030) when the annealing process is completed.
FIG. 3 is a graph showing a difference between the semiconductor device capacitance acquired through an annealing process of FIG. 1 and the capacitance without an annealing process.
Referring to FIG. 3, the semiconductor device capacitance "A" acquired through the PH.sub.3 annealing process is higher than the capacitance "B" acquired without the PH.sub.3 annealing process. A conventional PH.sub.3 annealing process is performed at a high temperature (about 750.degree. C.) for 3 hours and uses PH.sub.3 of 1.5 l/min. Accordingly, this PH.sub.3 annealing process taking a long time, results in lower yield. The time for flowing process gas practically takes 50% and more out of total time for performing a conventional PH.sub.3 annealing process. Since the process is performed by continuously supplying the process gas, a lot of the process gas can be wasted. That is, PH.sub.3 of 270 l is used while performing one time of the annealing process.
Consequently, a conventional a semiconductor device manufacturing process has drawbacks such as a long process time, low yield, and waste of process gas.